In a signal processing circuit for data compression process of motion pictures in a display, the data of motion pictures are compressed to be coded. Usually, continual frame data of motion pictures have intensive correlations, so that one of the data compression processes uses differences between two continual flame data as motion picture information. In more detail, the rear emotion compensation process and dispersive cosine translation (DCT) process in the data compression process.
In the motion compensation process, moving objects in one frame are detected, and amounts of the moving paths thereof between the continuous frames are calculated to be coded, and then the differences of amounts of the moving paths thereof are calculated to be used as motion picture information. The motion picture information is obtained by the following formula: EQU .SIGMA..vertline.X.sub.j -Y.sub.k .vertline. (1)
where X.sub.j and Y.sub.k are pixel data of the present and previous frames, respectively.
In the DCT process the frame data are transformed to be frequency components to be motion picture information obtained by the following formula: EQU .SIGMA.X.sub.j Y.sub.k ( 2)
In addition, there is another process of the DCT process called as fast cosine transformation (FCT) process. In the FCT process, butterfly arithmetic processes are carried out.
If there is little correlation between continuous frames, an inner and inter frame adaptation forecast process is used. The inner and inter frame adaptation forecast process is obtained by the following formula: EQU .SIGMA.(X.sub.j -Y.sub.k).sup.2 ( 3)
A first conventional signal processing circuit includes a data memory, a program memory, a register, first to third selecting circuits,- a multiplier, a shift register, an arithmetic circuit (an arithmetic logic unit), an accumulator, and a parallel logic unit.
In operation, data are supplied to the multiplier from a first data bus and the first selecting circuit connected with a second data bus, and arithmetic process of the supplied data is carried out. The result of the arithmetic process is supplied to the accumulator in which accumulation process is carried out. The result of the accumulation process is supplied to the first data bus, the arithmetic circuit and the second selecting circuit. On the other hand, the following arithmetic process is carried out independently with the above mentioned arithmetic process. Data for one arithmetic process stored in the data memory 4 are stored temporally in the register. The third selecting circuit selectively supplies the parallel logic unit with either the content of the register or that of the second data bus supplied from the program memory. The parallel logic unit 10 supplies the data memory through the first data bus with both an output of the third selecting circuit and the content of the data memory. Desired picture arithmetic processes are carried out by repeating such processes above mentioned.
A second conventional signal processing circuit includes a data memory, a multiplier, an arithmetic circuit (an arithmetic logic unit), an accumulator, a register and a barrel shifter.
In operation, data stored in the data memory are supplied to the barrel shifter, the arithmetic circuit and the multiplier in parallel through first and second data buses. Then, predetermined arithmetic processes are carried out respectively, and the results are stored in the register. The contents of the register are supplied to both the accumulator and a third data bus. Such series of processes are carried out simultaneously at either pair of the accumulator and the barrel shifter, the accumulator and the arithmetic circuit, and the accumulator and the multiplier, by conducting one instruction.
According to the conventional signal processing circuits, however, there is a disadvantage in that it takes a lot of steps to carry out arithmetic processes. In the first conventional signal processing circuit, it is impossible to carry out arithmetic processes of the motion compensation process and the inner and inter adaptation forecast by one instruction. In the second conventional signal processing circuit, data are rewritten to a data memory in each time after the arithmetic process, so that it takes more steps corresponding to data accessing to the data memory.